Technology

UPMC Technology: Architecture

Control unit - The heart of the UPMC Architecture

The control unit architecture in the below UPMC block diagram Fig.1 serves as a universal platform to design a single or multi loop control circuit. It includes an analog front-end (AFE) and digital Custom Logic building blocks as the main modules. The logic and the analog front-end blocks are highlighted in green and yellow respectively.

Their interconnection can be flexible and modified to suit control method and scheme of control circuit. In general, the control loop is powered through the common AFE Module followed by individual Digital Filter blocks (Proportional-Integral-Differential-Feed-Forward [PIDF] Module) and individual Pulse Sequence Generator blocks (PSG Module).


UPMC architecture
Figure #1

A key feature is that each control loop accomplishes the task of the highly tailored controller independent of the others, and works in parallel at a device clock rate up to 200MHz in the case of the IDC2000 IC implementation.

The present silicon implementation of the UPMC named IDC2000 (Integrated Digital Control) includes a IC family of up to 11 independent control loops and pulse sequence generators implemented in hardware. This feature overcomes the bottleneck of a single processor that may limit the computing power required for the closed loop control algorithms (for one or more channels) and produces performance figures that are tens of times better than those of the equivalent state-of-the-art DSPs.

Another important feature of the UPMC is the ability of each loop to serve the dual control function. First, it achieves design objectives for load and line regulation and dynamic response in closed-loop control mode. Second, it modifies parameters of control loop on-the-fly during the design stage or during normal operation, to change the working regime while power circuit is operating. Each control loop can realize various methods of non-linear and linear closed-loop control. The choice of control methods (voltage mode, average and peak current modes) as well as scheme of control (single or multi-loop) is driven solely by the problem to be solved.


Now available!

PDK L3 New CD
The PDK-L-3.1, a software design tool for configuring the IDC2000 IC family.