Technology

The IDC2000 Technology

The IDC2000 IC family is based on the UPMC architecture implemented in a silicon of 0.18µ technology.

This family has the following specific structural differentiations as it is depictured in its Block Diagram as follows:

1. The PIDF and the PSG modules comprise up to 11 channels each one.
   1. Device Model IDC2080 11 channels
   2. Device Model IDC2040 5 channels
   3. Device Model IDC2020 3 channels
2. The Communication Unit in addition to the basic elements that contains the UPMC architecture has the additional elements:
   1. A configurable hardwired Power Line Carrier Module (PLC Module)
   2. A configurable Digital Phase Look Loop Module (DPPL Module)
   3. An RF interface

High-Level Block Diagram of the IDC2080
(the larger version of the IDC2000 family)

The IDC2000 IC Family Specifications & Features

Clock Frequency	up to 192MHz
Pulse Sequence Generator Module
Outputs (non sequential driven signals)	up to 11 independent + 11 slaved outputs
Output signal (by configurable state machine)	Pulse cycle sequence
Pulse cycle composition	Each cycle composed of up to 16 states with different widths
Pulse modulation methods	PWM, FM or any combination
Minimum pulse width	26.5 nSec
Pulse resolution without dithering (by 12-bit timer, 192Mhz)	5.3 nSec
Pulse resolution with dithering (5 bits)	0.16 nSec
Analog Inputs	up to 24 analog inputs
A/D converter	Pipeline 10 bit, Configurable scanning
Maximum sampling rate of single input	12 MSPS (depend on scanning priority)
Configurable sampling point control	Generated by 11 PSGState machines
Analog input features	Comparator, Negative and Differential amplifier, Temperature sensor, T&H, Configurable gain
Digital I/Os	up to 52 digital I/O (10 Schmidt triggered)

Digital hardware processing
Loop control	up to 11 hardware implemented PIDF Templates
Min. response time for external event	150 nSec
Min. total PIDF calculation time for 11 outputs	170 nSec (parallel calculations)
Min. total system response time to single input sample	900 nSec (additional 83nSec for each successive input sample)
Total processing time of 24 inputs	2.9 uSec (pipeline processing)
On-the-fly configuration adjustment	enabled
System support & supervision	DR8052 high performance RISC CPU
Flash Memory>	64 kB
Communication Interfaces
SPI
Parallel port	8bit to 24bit (depending on the application) up to 48MHz
UART	Two Half duplex  UARTs up to 1.5M bit/sec
Two Way PLC Modem	Input sensitivity: 10mV , Carrier Frequency 100KHz- 200KHz, 10 -10 BER ( S/N 6db), 2000-4000bit/sec
RF Modem
Typical applications	Control of multi channel/ multi phase DC-DC, DC-AC, AC-DC, AC-AC topologies
Control methods	Multi (or single) voltage (or current) loop control Average or Peak Current modes

Power Line Carrier Modem

The PLC communication modem embedded in the IDC2000 IC family is a two-way half duplex transmission based on Systel property spread-spectrum PLC method. Its main specifications are as follows:

1. Input sensitivity: 10mV
2. Carrier Frequency: 100KHz- 200KHz
3. 10^(-10) BER versus S/N 6db
4. 2 - 4 Kbits/sec rate

PLC Modem Functional Block Diagram

DPLL

The DPLL implemented in the IDC2000 is a property configurable digital phase lock loop module aimed at synchronization to the line zero cross in power electronic systems or for sensing communication signals in noisy environment.
The DPLL enables a jitter-free synchronization to the mains. It serves mainly as a packet synchronization means for the PLC communication but can be used for other applications (UPS, etc.).

DPLL Functional Block Diagram

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