Building Blocks of the UPMC Architecture
Analog Front End Module
The main functions of the AFE module are to execute analog-to-digital conversion of analog feedbacks and digital-to-analog conversion of reference signals. For these purposes the AFE module comprises two sub-modules: Analog to Digital Converters (ADC) Module and Analog Compare Module.
ADC Module
The ADC Module uses ADC cell fed through analog multiplexer (MUX) to digitize analog feedback and analog parameters arriving from analog inputs. Control of ADC Module and storage of converted data is performed by ADC Scanner module. It is a memory-based unit that uses an over-sampling method, thus the required signals are stored in a RAM and are ready to be used by each and every PIDF channel and/or also by CPU. ADC Scanner module is used to scan the ADC analog inputs, by using flexible scanning sequences, and is configured by CPU. Track & Hold devices in ADC Module are used for time related sampling and enable analog measurements at a precise timing requested from the PSG switching signals and at the desirable phase of the input signal to avoid the measuring at noise sections.
AFE Compare Module
The AFE Compare Module (ACM) is meant for magnitude comparison between analog input and reference signals. It includes the analog comparator used to generate analog external events for control of PSG module. This module can be used for the control of the inner loop of "current mode control" power supplies. The programmable analog voltage references are provided by the CPU or alternatively by the PIDF optionally combining with digital saw tooth from PSG via (Digital to Analog Converters (DAC). Selection of the source of the reference is served by programmable DAC Scanner.
PIDF Module
The PIDF Module is a configurable integrated digital filter engine with feed forward capability. The larger device of the IDC2000 implementation includes 11 hardware implemented programmable control loop PIDF controllers as shown in the picture. These PIDF controllers relieve the central processor from heavy computational task of the control algorithm. Each PIDF controller is a control unit that performs the numeric calculations required to close a digital control loop. The calculations normally use variables such as a reference signal (generally invoked by a CPU) and various feedback signals fed from the controlled circuit of the application (external feedback signals) through the AFE module. The output of PIDF module is data sent to PSG module. Each PIDF controller has all of the proportional, integral, differential gain, and feed forward elements (feed forward to anticipate the affects of sudden input changes). |
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The PIDF Module is also capable of performing linear interpolations of CPU written reference points in order to generate various types of controlled waveforms and provide multi loop control in combination of the PIDF controllers. IDF module is configured by means of the CPU and capable of non linear control by its support
Pulse Sequence Generator
The PSG module is an event driven engine generating configurable pulse sequence drive signals for a switching mode machine (power supply, motor driver, UPS, ballast, etc.). Each transition in the pulse sequence signal is dictated by an "external event" or an "internal event".
The external event source is outside the IDC and is received typically from a power section. Examples of external events are: voltage zero cross, current zero cross, current threshold cross in current mode control, etc. Internal events are generated inside the IDC and define the duration time of intervals in a pulse sequence signal.
An internal event dictates the end of the time intervals (or pulse sequence segments) that have constant value or calculated value. For example, the PIDF module dictates the interval that has a calculated value (can also be called "loop controlled" value). |
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In the picture is shown the larger device application of the IDC2000 devices which comprises 11 PSG channels with a number of events as follows:
- Internal events (5 events x 11)
- External events (14 events x2)
Gated events (6 events) |
The pulse sequence configuration is established by means of the CPU at wake up as with the other modules. The configuration establishes the interval that has a constant value (the value can be changed on-the-fly) using configurable state machine. The internal event is generated by digital comparison of timer value to digital data derived from a digital comparator or by timer overflow. The interval value (duration time) is equal to the division of the digital data by the timer configurable clock frequency. The PSG pulse sequence drive signals can also be synchronized to an external clock frequency.
The configurability of the PSG module structure enables control of the timer operation in relation to the requested pulse sequence group. Each pulse sequence signal generated (each PSG channel) includes one or more look up tables (LUTs) for its configuration. Each row (address) of a LUT defines one state of the configurable state machine and generates one interval of the pulse sequence signal. Consecutive intervals are generated by consecutive rows (addresses). Therefore, the number of the intervals is equal to the number of the states. The maximum possible number of states in a pulse sequence signal is 16. In addition, the configuration of the PSG module enables the synchronization between PSG channels, and the implementation of many other functions like: hold request generation, gated events generation, protections and resolution improvement by 5 bit using Systel's dithering method. |
Supervisory Unit (CPU)
The UPMC comprises on-board CPU module that performs the supervision and general management of low frequency tasks. It functions mainly as the system manager, rather than control loop controller: it coordinates, monitors, protects and assists in complicated numerical calculations. The CPU load the configuration parameters to all the logic engine registers and look up tables of the UPMC modules during the initialization process. In addition, it delivers parameters for on-the-fly modification of the control unit configuration, setting of reference levels for the control loops, managing PSG module and supports the PIDFs in the implementation of non-linear control.. The CPU also controls interface with the flash memory and various digital I/O ports. Is involved in the communication management mechanism in general and supports communication functions, including the PLC modem..
Communication unit
The UPMC on-board communication unit is intended for support of the remote and/or centralized management of the various power equipments through shared communication network. To support a wide range of modern communication technologies the UPMC includes for power management purposes the following embedded communication modules: Power Line Carrier (PLC), RF, UART. Support of other communication standards (like DALI) is achieved by software.
To enable jitter-free synchronization of various processes to the utilities “Power Line” the UPMC includes the Configurable Digital Phase Locked Loop (DPLL) module. It serves mainly as a packet synchronization means for the PLC communication but can be used for other applications (UPS, etc.).
The Digital Power Control Pioneers 
